The present invention relates to bit field operations and more particularly, to performing bit field operations using a peripheral device.
It is known for processors to perform bit field operations through mask and logical operations. Bit field operations are operations which manipulate a specific bit or group of bits within a word. Some processors speed these bit field operations by specialized bit field instructions within the processor instruction set.
Bit field instructions which perform the bit field operations involve more complicated operands than do most other processor instructions because bit field instructions involve variable sized operands that are located at arbitrary bit offsets within words. Examples of these operands are operands specifying the start and length of the bit field as well as operands relating to the location of the bit field in a register or in memory.
Providing the processor with hardware to interpret and execute the encoded bit field instructions may require increasing the size of the processor's instruction decoder to handle the bit field operations. Also, the processor hardware to execute the bit field instructions may require additional or wider data paths to accommodate the complex operands.
An example of a processor which executes a limited number of bit field instructions is available from NEC Electronics under the trade designation .mu.PD70320/322. The .mu.PD70320/322 processor provides an extract bit field operation and an insert bit field operation. The extract bit field operation extracts a bit field of a specified length from a memory location. The extracted bit field is right justified within a transfer register with any unused bits cleared. The byte offset of the destination bit field is determined by the contents of a register. The insert bit field operation inserts a bit field into a memory location. More specifically a right-justified bit field of a specified length is transferred from a register to a memory location. The offset of the destination bit field is determined by the contents of an offset register. The start of the bit field is then located using the bit offset operation. Bit fields using this instruction have no alignment requirements and can span one or more byte boundaries.
Another example of a processor which executes bit field instructions is a digital signal processor available from Motorola under the trade designation DSP 56156. This processor includes a bit field manipulation group of instructions. The group of instructions tests the state of any set of bits within a byte in a memory location and then sets, clears or inverts bits in the byte. Bit fields which can be tested include an upper byte and a lower byte in a 16-byte value. The carry bit of a condition code register contains the result of the bit test for each instruction. These bit field manipulation instructions are read modify write instructions and require two instruction cycles. Parallel data moves are not allowed with any of the bit field instructions. The bit field instructions include a bit field test low instruction, a bit field test high instruction, a bit field test and clear instruction, a bit field test and set instruction and a bit field test and change instruction.